As CMOS technology is continually scaled to smaller dimensions, process variations due to process control limitations as well as fundamental physical limits tend to increase. Embedded memories such as embedded SRAM are particularly susceptible to large process variations because of aggressive design rules and their small size compared to other digital logic. To deal with this large increase in process variations, memory circuit designers typically use overly conservative design approaches in order to achieve high parametric and functional yield.
For example, a designer may trade-off performance (e.g., speed) and/or power consumption for yield by designing a particular integrated circuit (IC) to function over a broad range of process variations, including both local (within each IC) and global (among ICs) variation. This results in a larger percentage of the ICs produced being operational (i.e., increased yield), but the sacrifices in performance and/or power consumption may be substantial in those ICs that are not subjected to the full range of process variations. Due to the statistical nature of process variations, the actual number of ICs experiencing substantial performance and/or power consumption degradation may be quite high.
FIG. 1 is a schematic diagram illustrating a conventional memory system 100 that reads/writes data in accordance with a word line (WL) pulse. The memory system 100 includes a memory 110, a built-in self-test (BIST) circuit 120, and a pulse width set module 130. BIST 120 tests all or a portion of the internal functionality of memory 110. Pulse width set module 130 sets the WL pulse width to be used for the read/write cycles in memory 110. Pulse width set module 130 may receive an external n-bit code from a system controller, or the like, indicating the desired WL pulse width.
As is well known in the art, the WL pulse width determines the length of time each read or write operation requires to complete, which directly affects both the performance and the power consumption of that memory. In general, an increased WL pulse width ensures a more accurate read/write operation, but operates more slowly and requires more power. In contrast, a decreased WL pulse width may be less accurate, especially over a broad range of process variations, but can operate faster and requires less power. Thus, setting the desired WL pulse width is often a design trade-off between memory performance and yield.
When a batch of ICs implementing memory system 100 is produced, one of the conventional post-fabrication techniques used to optimize memory performance and increase yield is to use post-silicon digital trimming. Typically, the external digital code used to control the WL pulse width (WL pulse width code) is set to achieve the target yield for a certain memory. Measurements are performed on a large sample of memories, and yield is determined for different WL pulse widths. The optimum WL pulse width is determined based on the target yield and is fixed for all the memories.
This approach has several limitations. One limitation is that the WL pulse width is fixed for all ICs based on extreme process variations. As discussed above, many if not most of the ICs do not experience such extreme process variation. Therefore, large performance loss and additional power consumption may affect a majority of ICs produced. Another limitation is that large testing time is required to measure the large sample sizes needed to accurately determine the value of the optimum WL pulse width for a given target yield.